ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter

The oversampling ratio (OSR) can be at most FS/(2 · FBW ) = 16. After examining the empirical SQNR limit versus OSR and modulator order [1], I saw that a single bit quantizer cannot meet the design specification, which leads me to consider a multi-bit quantizer. I chose to use a third order modulator with a 9-level quantizer, which can obtain at most 85dB SQNR. Considering SQNR degradation due to thermal noise and non-ideal amplifier characteristics, among others, the actual SQNR performance will be worse. The use of a multi-bit quantizer can increase the stability in high order modulators, and the odd number of quantizer levels in this design simplifies the design of the feedback digital-to-analog converter (DAC). Another option would be to use a fifth order modulator with 3-bit quantizer with an OSR of 8 to provide at most 78dB SQNR. The lower OSR allows the sampling frequency to be reduced to 320 MHz which will reduce dynamic power consumption at the expense of higher static power consumption in the two additional switched capacitor integrators. I believe that the additional complexity of a fifth order modulator is not required since in a deep sub-micron process, dynamic power consumption is not necessarily dominant.